By Panagiotis Dimitrakis
This publication describes the elemental applied sciences and operation ideas of charge-trapping non-volatile thoughts. The authors clarify the equipment physics of every equipment structure and supply a concrete description of the fabrics concerned in addition to the elemental homes of the expertise. sleek fabric houses used as charge-trapping layers, for brand new purposes are introduced.
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Extra resources for Charge-Trapping Non-Volatile Memories: Volume 1 – Basic and Advanced Devices
3 CT Flash Cells Charge-trapping memory (CTM) devices are as old as the FG MOSFET. It was first presented 1967 (Wegener et al. 1967) and it was presented as an accomplished memory device in the form of Metal-Nitride-Oxide-Semiconductor (MNOS) structure (Frohman-Bentchkowsky 1970). Carriers were injected and ejected through a TOX and stored at the intrinsic traps of a nitride layer, which is then named as charge trapping-layer (CTL). To improve retention and solve reliability issues, the silicon nitride layer in MNOS cells was covered by another silicon oxide layer and the new devices were referred to as MONOS cells.
Dimitrakis Finally, the thickness reduction of TOX in QD NVM allows to PGM the memory cell by DT injection current instead of FN meaning that the PGM speed is increased (Dimitrakis et al. 2013b). The first QD NVM devices were presented in 1995 IEDM conference (Tiwari et al. 1995) by a group from IBM, NY. This revolutionary work was followed by many papers highly cited articles (Tiwari et al. 1996; King et al. 1998; Wahl et al. 1999) where the QDs were made of group IV semiconductors, mainly Si and Ge.
IEEE, New York, NY, pp 760–762 Govoreanu B, Brunco DP et al (2005) Scaling down the interpoly dielectric for next generation flash memory: challenges and opportunities. Solid State Electron 49:1841–1848 Habrakena FHPM, Kuiper AET (1994) Silicon nitride and oxynitride films. Mater Sci Eng R Rep 12:123–175 Harrison P (2005) Quantum wells, wires and dots, 2nd edn. Wiley, New York, NY IEEE (1999) IEEE standard definitions and characterization of floating gate semiconductor arrays. IEEE, New York, NY ISSCC (2014) ISSCC 2014 trends ITRS (2013) International technology roadmap of semiconductors (Vol.
Charge-Trapping Non-Volatile Memories: Volume 1 – Basic and Advanced Devices by Panagiotis Dimitrakis